In recent semiconductor devices, a silicidation technique has been used to reduce the resistance of gate electrodes and source and drain regions.
In the silicidation technique, silicon in a gate electrode and a source and drain region is allowed to react with a high-melting-point metal, such as cobalt or nickel, to form a metal silicide layer on the gate electrode and the source and drain region.
In some cases, in addition to a field-effect transistor, a resistance element is formed on a chip. In the formation of the resistance element, for example, a polycrystalline silicon layer is patterned on a device isolation region, such as a trench isolation region. Thus, the polycrystalline silicon layer is patterned simultaneously with the patterning of a polycrystalline silicon film in the formation of a gate electrode. However, since the polycrystalline silicon layer is used as the resistance element, no metal silicide layer is formed on the patterned polycrystalline silicon layer.
Thus, Japanese Laid-open Patent Publication No. 2005-79290 discusses a technique in which a silicide block pattern formed of a SiN film having a thickness in the range of 5 nm to 20 nm and a SiO2 film having a thickness of 40 nm is formed on a metal silicide layer disposed on a polycrystalline silicon layer for use in the formation of a resistance element to prevent the formation of a silicide layer, thus providing a resistance element.
The SiN film is formed after a source and drain region is doped with an impurity. Thus, there is no block film preventing the implantation of a contaminant, an element having a large atomic weight, or a cluster ion in the impurity doping. A contaminant may therefore be implanted in the surface of a sidewall spacer. The contamination reduces the insulation resistance of a sidewall.
A natural oxidation film or a block film on a silicon substrate may be removed, for example, by wet etching using a hydrofluoric acid (HF) solution, before a high-melting-point metal is deposited on the silicon substrate to form a silicide layer. The wet etching may excessively etch the sidewall spacer. The over-etching deforms the sidewall spacer, causing lot-to-lot variations in the parasitic resistance of field-effect transistors.
Furthermore, in the wet etching, a high etch rate of the SiO2 film in the silicide block may cause lot-to-lot variations in etching depth. This causes lot-to-lot variations in the formation of a region in the polycrystalline silicon layer in which the metal silicide layer is to be formed, and eventually causes lot-to-lot variations in the resistance of the resistance element.